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Freescale Semiconductor /MK61F15WS /DDR /CR53

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Interpret as CR53

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)CLKDISCS 0RESERVED 0RESERVED0CRTLUPDMN 0RESERVED 0CTRLUPDMX0RESERVED

CLKDISCS=0

Description

DDR Control Register 53

Fields

CLKDISCS

DRAM Clock Disable for chip select

0 (0): Memory clock active

1 (1): Memory clock disabled
RESERVED

Reserved
RESERVED

Reserved
CRTLUPDMN

DFI CRTLUPD Minimum
RESERVED

Reserved
CTRLUPDMX

DFI CRTLUPD Minimum
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data